Dynamic logic circuits are based on electrical charge storage and transfer. One or more nodes are used to store electrical charge. The nodes are typically charged to one voltage level (i.e., precharged) during a precharge operation, and selectively charged (e.g., discharged) to another voltage level during a subsequent evaluation operation dependent upon input signals. For example, nodes of dynamic logic circuits are commonly precharged to a high voltage level when a synchronizing clock signal is at one voltage level, and selectively discharged to a low voltage level dependent upon the input signals when the clock signal transitions to another voltage level.
Self-resetting logic circuitry is a type of dynamic logic circuitry in which pulses control logic operations. In self-resetting logic circuitry, one or more nodes are typically precharged between pulses, and logic operations are performed during the pulses. Widths of the pulses are typically selected such that correct results are produced by the self-resetting logic circuitry. In general, reducing the widths of the pulses typically improves performance.
A typical pulse generator used in self-resetting logic circuitry generates pulses from a single edge of a clock signal (e.g., a rising edge transition of the clock signal or a falling edge transition of the clock signal). The typical pulse generator produces pulses having a width that is a fixed maximum at relatively low frequencies of the clock signal, and generally decreases as the frequency of the clock signal increases.
FIG. 1 is a diagram of a known pulse generator circuit 100 for generating a pulse signal PCLK from a clock signal CLK. The pulse generator 100 generates pulses from rising edge transitions of the clock signal CLK, and includes an AND gate 102 and n inverters in series, three of which are shown in FIG. 1 and labeled 104A, 104B, and 104C (n is typically an odd integer greater than or equal to 3).
An “A” input of the AND gate 102 receives the clock signal CLK. The clock signal CLK propagates through the n inverters 104 in series and arrives at a “B” input of the AND gate 102. While propagating through the n inverters 104 in series, the clock signal CLK experiences a delay time equal to “tDELAY” as indicated in FIG. 1. The AND gate 102 produces the PCLK signal by logically ANDing the signals at the A and B inputs (i.e., by logically ANDing the A and B input signals). As indicated in FIG. 1, the AND gate 102 has an internal propagation delay time equal to “tAND.”
FIG. 2 is a timing diagram showing various signals in the known pulse generator circuit 100 of FIG. 1 versus time. In FIG. 2, the clock signal CLK alternates between a low voltage level and a high voltage level, and remains at the high voltage level for an amount of time greater than the delay time tDELAY of the n inverters 104 of FIG. 1. In other words, the clock signal CLK has a “high” time of “tHIGH” that is greater than the delay time tDELAY of the n inverters 104 of FIG. 1. The A input signal to the AND gate 102 is the clock signal CLK, and the B input signal is the clock signal CLK inverted and delayed in time by the delay time tDELAY of the n inverters 104. The output signal PCLK produced by the AND gate 102 is a series of positive pulses having pulse width times “tPW” as indicated in FIG. 2. Each of the positive pulses is generated the delay time tAND after a rising edge of the clock signals CLK, and has a pulse width of tDELAY.
FIG. 3 is a timing diagram showing various signals in the pulse generator circuit 100 of FIG. 1 versus time, wherein the high time tHIGH of the clock signal CLK is less than the delay time tDELAY of the n inverters 104 of FIG. 1. The pulse width times tPW of the PCLK signal in FIG. 3 (i.e., produced at a higher frequency of the clock signal CLK) are significantly less than the pulse width times tPW in FIG. 2 (i.e., produced at a lower frequency of the clock signal CLK).
In general, when the high time tHIGH of the clock signal CLK is greater than or equal to the delay time tDELAY (i.e., at relatively low frequencies of the clock signal CLK), the pulse generator circuit 100 of FIG. 1 produces signal PCLK with pulses having a width tPW that is a fixed maximum of the delay time tDELAY. When the high time tHIGH of the clock signal CLK is less than tDELAY (i.e., at relatively high frequencies of the clock signal CLK), the pulses of the PCLK signal have widths tPW that are less than tDELAY, and decrease with increasing frequency of the clock signal CLK.
A problem arises in the pulse generator circuit 100 of FIG. 1 in that the width of the pulses of the PCLK signal cannot be increased beyond the fixed maximum of tDELAY. In a device including dynamic logic circuitry using the pulse generator 100, should the maximum width of the pulses of the PCLK signal be insufficient to produce correct operation of the dynamic logic circuitry, the faulty device typically cannot be repaired.
The pulses of the signal PCLK in FIG. 3 (i.e., produced at a higher frequency of the clock signal CLK) are also delayed in time with respect to the clock signal CLK to a greater degree than are the pulses of the signal PCLK in FIG. 2 (i.e., produced at a lower frequency of the clock signal CLK). In general, when the high time tHIGH of the clock signal CLK is greater than or equal to the delay time tDELAY (i.e., at relatively low frequencies of the clock signal CLK), the pulse generator circuit 100 of FIG. 1 produces signal PCLK with pulses delayed in time from leading edges of the clock signal CLK by delay time tAND. As the high time tHIGH of the clock signal CLK is decreased below the delay time tDELAY, the pulses of the PCLK signal are increasingly delayed in time relative to the clock signal CLK.
Another problem arises in the pulse generator circuit 100 of FIG. 1 in that at higher frequencies of the clock signal CLK, the variable time delay between the pulses of the PCLK signal and the clock signal CLK may negatively affect synchronization between dynamic logic circuitry using the typical pulse generator and other logic circuitry controlled by the clock signal CLK.